In synchronous circuits, memory elements, such as latches, capture data and change state according to a clock signal. Each memory element may receive a distinct copy of the clock signal, and properly synchronizing the elements may entail careful alignment of the edges of each clock signal copy. Clock drivers, buffers, repeaters, routing, and other clocking resources that distribute the signals are allocated a significant amount of the power and floorplanning budget because variations in the clock edges across memory elements affect performance. In an example, clock skew between a sending latch and a receiving latch affects the amount of time available for combinational logic between the latches, and excessive skew may cause the data to arrive at the receiving latch too late in the cycle to be accurately captured. In this way, the robustness of the clock tree may directly affect the maximum speed of a given circuit.
To meet the demands for faster computations, lower power, and smaller circuits, some designs use asynchronous circuits, where data is processed and captured independent of a clock. While portions of a circuit may have their own local clocks, data may be exchanged between portions independent of the local clock domains. Thus, a global clock and the associated clock distribution circuitry may be avoided. While some asynchronous designs may be more complex than their synchronous counterparts, the improved performance and potential lower power may justify the complexity.